1. Field of the Invention
The present invention relates to an electrical interconnection arrangement for making connection between electronic devices and, more particularly, to making electrical connection between chip die and the next level of carrier.
2. Background and Related Art
One of the problems encountered with some semiconductor chip die connections to the next level of packaging is the high stress on the interconnections caused by coefficient of thermal expansion (CTE) mismatch. The CTE thermal mismatch is particularly large where the chip die is connected to laminate chip carriers made of material similar to an epoxy circuit board material. As circuit densities in chip dies increase, so does the heat generated by these dies thereby compounding the problem with larger temperature variations in its thermal cycle. In addition, certain applications, such as flip chip applications, have required encapsulation to ensure a reliable flip chip interconnection in the solder joints. Such encapsulation typically employs a high strength epoxy which acts to bond the chip die to the laminate chip carrier. This bonding of chip die to chip carrier reduces solder joint stress during thermal cycling but causes the chip die itself to be put under cyclical high internal stress eventually leading to chip cracking, delamination and device breakdown.
The above described high internal stresses on the chip die are generally attributed to the fact that the bonding of chip die to laminate chip carrier acts to cause this composite of materials to act like a “bimetallic” element wherein the composite bends upon heating due to the different CTE of the materials. As a result of the large thermal mismatch between the die and laminate chip carrier, the cyclical bending over time causes device failure. In this regard, the CTE for a typical chip die may be in the order of 3 micro inches per inch per degree Centigrade while a typical laminate chip carrier is around six times that amount. Thus, although the use of encapsulation is to prevent the C-4 connections from detaching from fatigue and fracturing over thermal cycling, the bonding action of the encapsulation in itself acts to cause the chips to fracture and separate from the chip carrier.
In general, others have attempted to address the problems caused by CTE mismatch of materials in IC packaging by providing various interposing structures that attempt to reduce the mismatch of CTE. For example, multiple layers of materials with varying CTEs may be employed to form an interposing layer between one level of packaging and the next, with the layers having a gradation of CTEs such that the layer contacting one level of packaging is selected to have a CTE which more closely matches the CTE of that level while the layer contacting the next level of packaging has a CTE more closely matching that level while layers between may gradually reduce the difference. In addition, efforts have also been made to use interposing layers which are flexible in nature such as to reduce the stress on electrical interconnections during thermal cycling created by thermal mismatch. However, these various efforts typically rely on single or multiple layers of material which are either costly to fabricate or difficult to assemble, and are not totally effective in their purpose. More often, these layers are between ceramic chip carriers and circuit board or card.